Decoupling capacitors (DECAPs) are often used with integrated circuits, such as CMOS devices, in order to reduce power supply noise and otherwise keep power provided to the CMOS devices within specification. A typical arrangement of decoupling capacitors can be seen in FIG. 1, in which a plurality of decoupling capacitors are electrically connected in parallel with one another.
Unfortunately, with the arrangement shown in FIG. 1, time dependent dielectric breakdown (TDDB) of these decoupling capacitors frequently limits the power supply voltage (VDD) utilized in the CMOS devices. One solution to this problem is to increase the thickness of the dielectric utilized in the decoupling capacitors. However, this solution leads to lower density of capacitors as well as decreased performance.
Accordingly, it is desirable to provide a decoupling capacitor arrangement to improve TDDB reliability without sacrificing overall performance of the integrated circuit. In addition, it is desirable to provide a decoupling capacitor arrangement to provide a higher and more stable VDD to the CMOS device. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.